Overview

We are seeking a Senior Formal Verification (FV) Engineer to own the formal verification environment for our next‑generation, high‑performance Out‑of‑Order (OoO) RISC‑V Vector Unit (VU). Reporting directly to the Vector Unit Verification Lead, this is a highly technical individual contributor role. You will be the dedicated formal expert for the VU team, responsible for designing scalable formal testbenches, writing mathematical properties, and ensuring the absolute algorithmic and architectural integrity of our vector pipeline. You will work side‑by‑side with VU microarchitects to hunt down deep corner‑case bugs and achieve formal sign‑off on high‑complexity arithmetic and execution blocks.

Key ResponsibilitiesBlock‑Level Execution & Convergence Engineering (90%)

• End‑to‑End Testbench Ownership: Design, deploy, and maintain robust formal verification environments for complex Vector Unit sub‑blocks (e.G., Vector Execution Pipelines, Vector Register File/Ren...