Aistech Space in Barcelona is looking for an experienced FPGA Design Engineer to lead the development of next-generation image acquisition systems. This role involves transforming high-speed sensor data into actionable insights through VHDL logic and hardware acceleration.

Key responsibilities include Xilinx RTL development, implementing high-speed connectivity protocols, and architecting low-latency data paths. The successful candidate will thrive in an agile setting and contribute to innovative environmental monitoring solutions.