Responsible for all aspects of Physical design (Place & Route, STA analysis, PI/SI analysis, physical verification, DFR design and verification, DFM design and verification, physical design data delivery.), Full custom and its implementation in a team environment performing full-custom analog and mixed-signal layout of next generation high-speed interfaces and signal integrity systems (aka SerDes, PHY) in deep submicron FinFET technologies.

Job Requirements:

• Experienced in synthesis, Place & Route, timing closure, PV, PI, PPA improvement. etc and major EDA tools including Cadence, Synopsys, and Mentor tools.
• Implementation of multimillion gate SoC designs in cutting edge process technologies (16nm,14nm & below). Experience in Finfet technologies is a must.
• Expertise in floor planning including power grid design to meet EMIR specifications.
• Good understanding of timing concepts, Experience in Generating and Implementing E...