Cadence is seeking a Physical Design Senior Principal Hardware Engineer to drive solutions from synthesis to tape-out, with expertise in floorplanning, clock construction, placement, routing and signoff.

You will collaborate with RTL, DFT and Architecture teams, own blocks/SoCs to tape-out, and contribute to tool development for higher design quality in Cadence’s HPC-focused emulation-acceleration platform; position based in Cadence’s US offices.