MaxLinear, Inc. in Singapore is seeking a Senior Principal SOC Design Engineer to join our VLSI group. This role involves pre-silicon RTL coding and SOC integration, requiring deep knowledge of design architecture and robust code development.

The ideal candidate will have a Bachelor’s or Master’s in Electronics Engineering and at least 18 years of experience, along with expertise in VHDL and Verilog coding. Strong skills in verification and team collaboration are essential for success in this position.