Senior RTL Design Engineer

_corporate_fare_ Google _place_ Mountain View, CA, USA

**Advanced**

Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain.

**Minimum qualifications:**

+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
+ 10 years of experience with IP Development or Integration.
+ Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language).
+ Experience with a scripting language (e.g., Python or Perl).

**Preferred qualifications:**

+ Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
+ Experience with ASIC design methodologies for clock domain checks, reset checks, and low power design.
+ Knowledge of one of these areas: proc...