Position Overview:
We are looking for a highly experienced Senior Engineer in So C Design Verification to join our dynamic team and contribute to the development of cutting-edge So C solutions.
As a Senior Engineer in So C Design Verification, you will play a key role in leading the SV/UVM based Subsystem and So C verification strategy, planning, and execution for complex So C projects. You will collaborate closely with cross-functional teams to ensure the highest quality and performance standards for our So C products. This role requires deep technical expertise, leadership skills, and a passion for solving challenging verification problems.
Key Responsibilities :
Architect and develop reusable testbenches and Verification IP (VIP) using System Verilog and UVM to create scalable verification environments from scratch.
Drive coverage closure , ensuring thorough functional coverage and code coverage across all So C components.
Implement and manage SV assertions and cov...