We are looking for an experienced Synthesis Methodology Engineer to own and drive RTL synthesis methodologies across our AI SoC development projects. You will be responsible for developing, maintaining, and optimizing synthesis flows, evaluating new EDA tools, and enabling efficient implementation across multiple technology nodes.

You will collaborate closely with Design, Backend, CAD, and EDA vendors to improve design productivity and quality.

• Synthesis Flow Ownership: Develop, maintain, and optimize RTL synthesis flows using Synopsys Design Compiler to support ASIC/AI SoC development.
• Synthesis Methodology: Design and improve synthesis methodologies, automation, and reusable workflows across multiple projects and technology nodes.
• RTL Synthesis: Perform RTL synthesis for AI/NPU-related blocks while ensuring quality, performance, and design convergence.
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