Join Astera Labs as a Senior Design Verification Engineer, where your skills in C/C++ and UVM will enhance AI connectivity solutions.

In this role, you will leverage your technical expertise in verification methodologies and programming to impact state-of-the-art AI infrastructure projects. Working independently, you'll create detailed test plans and collaborate with RTL designers to debug and ensure product quality. Experience with CXL®, PCIe®, and other protocols is essential for success.

Key Responsibilities:
• Develop comprehensive UVM-based test plans and sequences
• Integrate C/C++ for RTL simulation and debugging
• Use Perl or Python for automating verification tasks
• Employ Verification IPs for varied communication protocols
• Generate user-controlled random constraints for validation

Requirements:
• BS in Electrical Engineering; Master's degree preferred
• At least 2 years in complex SoC developm...