Link-Worldwide is looking for a Senior VLSI/Layout Engineer to work on essential IP design and verification tasks in a hybrid role based in Mexico. The job responsibilities include utilizing Cadence VLE/VXL and Calibre DRC/LVS tools, collaborating with design engineers for layout design, and adhering to verification protocols to ensure compliance.

The ideal candidate should have a minimum of 6 years of experience with relevant tools, a solid understanding of circuit design, and strong communication skills. A BE or MTech in Electronic/VLSI Engineering or a related field is required. #J-18808-Ljbffr