Lead ASIC DFT Engineer

Location: Remote (Must align with PST) Pay Rate: $80–$90/hr (W2) Visa: USC, GC, EAD (No OPT/CPT)

Overview

Senior-level ASIC DFT expert responsible for end-to-end DFT architecture, implementation, verification, and silicon debug for complex ASIC/SoC designs.

Key Skills (Must Have)

Scan, ATPG, MBIST, LBIST

Timing Simulation, SDF, SDC

Pattern Retargeting / Porting

Diagnosis, DRCs

Tools: TetraMax, DFTMax

Experience

10+ years in ASIC DFT (hands-on)

Responsibilities

Lead DFT architecture, implementation & sign-off

Drive scan insertion, scan chains & compression flows

Own MBIST/LBIST integration and debug

Perform silicon debug, failure analysis & root cause

Develop DFT constraints (SDC) & timing analysis

Support ATPG generation, simulation & ...