Responsibilities
Testbench and test sequence development for verification of new controller technologies and features Functional coverage planning, coverage item coding, and test suite augmentation to achieve Functional Coverage Regression test development, monitoring, debug/triage, and correction to test environment, sequences, debug of controller RTL design Development & support of Verification environment scripting and capabilities Qualifications
Bachelors Degree or above in EE/CS, at least 4-6 years experience with HDL logic Design-Verification System Verilog / UVM testbench, Verilog/System Verilog logic design/RTL fluency a must Pre-existing Experience / familiarity with PCI-Express controller and protocol required Working experience with Python and TCL scripting languages preferred Rambus is a global company that makes industry-leading memory interface...