Responsibilities
MaxLinear is seeking a SOC Verification Engineer to join our VLSI group. You will be responsible for pre-silicon RTL verification of block, subsystem and top level SOC. With deep understanding of design architecture and meticulous attention to details, you will develop reusable testbench and verification environment in SV-UVM. In this role , you will focus on:- Pre-silicon RTL verification of block, IP and top level SOC using best-in-class verification methodology Develop reusable testbench and verification environment in SV UVM Create verification plan from specification and in coordination with architects Create directed and constrained random test case to verify functional correctness and performance of the design Own and debug failures in simulation to root-cause problems Co-work with Architecture/ Design/Validation/SW teams. Own cross functional debug and drive issues to closure Qualifications
Bachelor Degree in Electronics Engineering with 6 years or Master...