STA Engineer – 5+ Years Experience
We are seeking an experienced

STA (Static Timing Analysis) Engineer

with 5+ years of expertise in ASIC/SoC timing analysis and closure for advanced technology nodes. The ideal candidate should possess strong knowledge of timing methodologies, signoff flows, and timing convergence across full-chip and block-level designs.
Key Responsibilities
Perform block-level and full-chip Static Timing Analysis (STA).
Handle timing closure for setup, hold, recovery, and removal checks.
Work on MMMC timing environments and timing signoff methodologies.
Analyze and debug timing violations across different corners and modes.
Collaborate closely with Physical Design, RTL, DFT, CTS, and ECO teams.
Drive timing closure during synthesis, placement, CTS, and routing stages.
Perform constraint validation and SDC generation/debugging.
Support ECO implementation and timing verification.
Analyze and resolve clock-domain crossi...