Job Title: STA Engineer

Location: Santa Clara, CA

Duration: Full Time, Permanent (Onsite)

Job Description

We are seeking a Timing Implementation Engineer with strong expertise in Static Timing Analysis (STA) and RTL Synthesis for high-speed interfaces such as PCIe. This role is focused on implementation and timing closure, not design, and requires hands-on experience driving block-level and full-chip sign-off from RTL synthesis through tapeout.

Key Responsibilities

Perform block-level and full-chip STA across the project lifecycle, from early investigation to final tapeout.

Execute RTL synthesis flows, ensuring optimal QoR (Quality of Results) and alignment with timing constraints.

Write and develop timing constraints (SDC) for PCIe and other high-speed interfaces.

Build and enhance timing methodology and infra...