We are looking for a digital design engineer with DFT capabilities

1. Experience: 5+ years of hands-on experience in DFT architecture and implementation for SoC/ASIC.
2. Skilled in different types of DFT structures, including scan (Stuck-At, At-Speed, Path-Delay), scan compression, boundary scan and MBIST.
3. Experience in creating and implementing hierarchical DFT architecture in complex SoC.
4. Experience in Low-Power DFT and MBIST.
5. Experience in test time and test coverage analysis for scan and MBIST patterns.
6. Experience in working with test engineering team to bring up production test program.
7. Extensive knowledge of timing concepts and constraint development.
8. Experience in developing scan ATPG and MBIST test benches and simulation in pre/post-layout environments.
9. Experience in RTL is required.