Technical Lead - Design Verification Experience: 8 Years Location: Bengaluru We are seeking a highly skilled and experienced Senior Design Verification Engineer to join our SoC/ASIC verification team in Bangalore. The ideal candidate will have a deep understanding of the verification lifecycle, from test planning to coverage closure, and be able to independently drive complex verification tasks for IP, subsystem, or full-chip level designs. Key Responsibilities: Develop and execute test plans for IP/subsystem/full-chip level verification. Build and maintain constrained-random and directed testbenches using SystemVerilog and UVM. Drive functional coverage closure and ensure high-quality tape-outs. Collaborate with RTL designers, architecture, and software teams to understand design features and define test scenarios. Participate in code reviews , debug RTL/testbench issues, and file bug reports. Use industry-standard tools like VCS, QuestaSim, Verdi, Synopsys, Cadence, or Mentor toolcha...