Perform back‑end implementation using deep sub‑micron technology.
Block and chip level floorplanning.
Pre‑wire and timing‑optimization tasks.
Data preparation of IP such as analog and RF macros.
Detailed place and route for both block macros and chip level, including clock‑tree synthesis, power routing, timing‑driven placement and routing, signal integrity analysis, and design for yield techniques.
Generation of detailed parasitic information.
Static and dynamic rail analysis.
Signoff static timing analysis.
Physical verification, including LVS and DRC.
Maintenance of PnR flows.
Development of new flow features and tool evaluations.
Technical Skills
High level scripting in TCL, Perl, and Python for maintaining and developing implementation flows.
Advanced knowledge of synthesis, floorplanning, clock tree synthesis, power routing an...
Ready to Apply?
Join thousands of Americans building their careers