Drive innovation as a UVM Verification Expert at Synopsys, focusing on cutting‑edge memory interface IP designs. Utilize your expertise in SystemVerilog to craft high‑performance verification environments. Step into this Senior Staff position where your role is pivotal in developing robust test plans and analyzing complex digital systems.

Your mentorship will enhance team capabilities, and your collaboration will ensure clarity and alignment across projects. You will directly contribute to advancing verification methodologies that enhance product delivery. Your expertise will significantly advance Synopsys' IP products and market reputation.

Key Responsibilities

• Create detailed functional coverage models for memory IP
• Design test cases to verify RTL PHY functionality
• Collaborate in technical reviews with architecture teams
• Resolve abstract verification challenges with advanced techniques
• Integrate virtual prototyping...