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Static Timing Methodology Development for Gate Level Timing Sign off

IBM β€’ Bangalore, India, India

Excellent opportunity in the United States...

Featured

Formal Verification Engineer

Scaledge Technology β€’ Bengaluru, Karnataka, India

Excellent opportunity in the United States...

VLSI - RTL/ASIC&SOC frontend Design

HCLTech β€’ India, India, India

Excellent opportunity in the United States...

Senior Engineer – ASIC Design Verification

eInfochips (An Arrow Company) β€’ Bhopal, Madhya Pradesh, India

Excellent opportunity in the United States...

Engineer, Quality

LeadSoc Technologies Pvt Ltd β€’ Bengaluru, Karnataka, India

Excellent opportunity in the United States...

Senior Engineer – ASIC Design Verification

eInfochips (An Arrow Company) β€’ Udaipur, Rajasthan, India

Excellent opportunity in the United States...

Principal Engineer – Chip Design Back End

Toshiba Software (India) Pvt. Ltd. β€’ Bengaluru, Karnataka, India

Excellent opportunity in the United States...

Senior Engineer – ASIC Design Verification

eInfochips (An Arrow Company) β€’ Bharatpur, Rajasthan, India

Excellent opportunity in the United States...

Lead - STA Engineer

ACL Digital β€’ Bengaluru, Karnataka, India

Excellent opportunity in the United States...

Senior Engineer – ASIC Design Verification

eInfochips (An Arrow Company) β€’ Vijayawada, Andhra Pradesh, India

Excellent opportunity in the United States...